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stm32 /stm32f1 /STM32F102 /FLASH /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LATENCY 0 (HLFCYA)HLFCYA 0 (PRFTBE)PRFTBE 0 (PRFTBS)PRFTBS

Description

Flash access control register

Fields

LATENCY

Latency
HLFCYA

Flash half cycle access enable
PRFTBE

Prefetch buffer enable
PRFTBS

Prefetch buffer status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32