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stm32 /stm32f1 /STM32F103 /ETHERNET_MMC /MMCTIR

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Interpret as MMCTIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TGFSCS)TGFSCS 0 (TGFMSCS)TGFMSCS 0 (TGFS)TGFS

Description

Ethernet MMC transmit interrupt register (ETH_MMCTIR)

Fields

TGFSCS

Transmitted good frames single collision status
TGFMSCS

Transmitted good frames more single collision status
TGFS

Transmitted good frames status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32