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stm32 /stm32f2 /STM32F217 /SYSCFG /CMPCR

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Interpret as CMPCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMP_PD)CMP_PD 0 (READY)READY

Description

Compensation cell control register

Fields

CMP_PD

Compensation cell power-down
READY

READY

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32