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stm32 /stm32f3 /STM32F3x8 /ADC1_2 /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MULT0DELAY0 (DMACFG)DMACFG 0MDMA 0CKMODE 0 (VREFEN)VREFEN 0 (TSEN)TSEN 0 (VBATEN)VBATEN

Description

ADC common control register

Fields

MULT

Multi ADC mode selection
DELAY

Delay between 2 sampling phases
DMACFG

DMA configuration (for multi-ADC mode)
MDMA

Direct memory access mode for multi ADC mode
CKMODE

ADC clock mode
VREFEN

VREFINT enable
TSEN

Temperature sensor enable
VBATEN

VBAT enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32