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stm32 /stm32f3 /STM32F3x8 /GPIOC /BRR

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Interpret as BRR

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https://regviz.com/r/stm32/stm32f0/STM32F0x0/GPIOA/BRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

Port bit reset register

Fields

BR0

Port x Reset bit y
BR1

Port x Reset bit y
BR2

Port x Reset bit y
BR3

Port x Reset bit y
BR4

Port x Reset bit y
BR5

Port x Reset bit y
BR6

Port x Reset bit y
BR7

Port x Reset bit y
BR8

Port x Reset bit y
BR9

Port x Reset bit y
BR10

Port x Reset bit y
BR11

Port x Reset bit y
BR12

Port x Reset bit y
BR13

Port x Reset bit y
BR14

Port x Reset bit y
BR15

Port x Reset bit y

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32