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stm32 /stm32f3 /STM32F3x8 /SPI1 /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CPHA)CPHA 0 (CPOL)CPOL 0 (MSTR)MSTR 0BR0 (SPE)SPE 0 (LSBFIRST)LSBFIRST 0 (SSI)SSI 0 (SSM)SSM 0 (RXONLY)RXONLY 0 (CRCL)CRCL 0 (CRCNEXT)CRCNEXT 0 (CRCEN)CRCEN 0 (BIDIOE)BIDIOE 0 (BIDIMODE)BIDIMODE

Description

control register 1

Fields

CPHA

Clock phase
CPOL

Clock polarity
MSTR

Master selection
BR

Baud rate control
SPE

SPI enable
LSBFIRST

Frame format
SSI

Internal slave select
SSM

Software slave management
RXONLY

Receive only
CRCL

CRC length
CRCNEXT

CRC transfer next
CRCEN

Hardware CRC calculation enable
BIDIOE

Output enable in bidirectional mode
BIDIMODE

Bidirectional data mode enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32