stm32 /stm32f4 /STM32F401 /TIM2 /CR1

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Interpret as CR1

31282724232019161512118743000000000000000000000000000000000000000000 (CEN)CEN0 (UDIS)UDIS0 (URS)URS0 (OPM)OPM0 (DIR)DIR0CMS0 (ARPE)ARPE0CKD

Description

control register 1

Fields

CEN

Counter enable

UDIS

Update disable

URS

Update request source

OPM

One-pulse mode

DIR

Direction

CMS

Center-aligned mode selection

ARPE

Auto-reload preload enable

CKD

Clock division

Links

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