stm32 /stm32f4 /STM32F405 /FSMC /SDTR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SDTR2

31282724232019161512118743000000000000000000000000000000000000000000TMRD0TXSR0TRAS0TRC0TWR0TRP0TRCD

Description

SDRAM Timing register 2

Fields

TMRD

Load Mode Register to Active

TXSR

Exit self-refresh delay

TRAS

Self refresh time

TRC

Row cycle delay

TWR

Recovery delay

TRP

Row precharge delay

TRCD

Row to column delay

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