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stm32 /stm32f4 /STM32F407 /FSMC /SDRTR

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Interpret as SDRTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CRE)CRE 0COUNT0 (REIE)REIE

Description

SDRAM Refresh Timer register

Fields

CRE

Clear Refresh error flag
COUNT

Refresh Timer Count
REIE

RES Interrupt Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32