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stm32 /stm32f4 /STM32F411 /RCC /APB1RSTR

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Interpret as APB1RSTR

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https://regviz.com/r/stm32/stm32f4/STM32F401/RCC/APB1RSTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (TIM3RST)TIM3RST 0 (TIM4RST)TIM4RST 0 (TIM5RST)TIM5RST 0 (WWDGRST)WWDGRST 0 (SPI2RST)SPI2RST 0 (SPI3RST)SPI3RST 0 (UART2RST)UART2RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (I2C3RST)I2C3RST 0 (PWRRST)PWRRST

Description

APB1 peripheral reset register

Fields

TIM2RST

TIM2 reset
TIM3RST

TIM3 reset
TIM4RST

TIM4 reset
TIM5RST

TIM5 reset
WWDGRST

Window watchdog reset
SPI2RST

SPI 2 reset
SPI3RST

SPI 3 reset
UART2RST

USART 2 reset
I2C1RST

I2C 1 reset
I2C2RST

I2C 2 reset
I2C3RST

I2C3 reset
PWRRST

Power interface reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32