mask register
| CCRCFAILIE | Command CRC fail interrupt enable |
| DCRCFAILIE | Data CRC fail interrupt enable |
| CTIMEOUTIE | Command timeout interrupt enable |
| DTIMEOUTIE | Data timeout interrupt enable |
| TXUNDERRIE | Tx FIFO underrun error interrupt enable |
| RXOVERRIE | Rx FIFO overrun error interrupt enable |
| CMDRENDIE | Command response received interrupt enable |
| CMDSENTIE | Command sent interrupt enable |
| DATAENDIE | Data end interrupt enable |
| STBITERRIE | Start bit error interrupt enable |
| DBCKENDIE | Data block end interrupt enable |
| CMDACTIE | Command acting interrupt enable |
| TXACTIE | Data transmit acting interrupt enable |
| RXACTIE | Data receive acting interrupt enable |
| TXFIFOHEIE | Tx FIFO half empty interrupt enable |
| RXFIFOHFIE | Rx FIFO half full interrupt enable |
| TXFIFOFIE | Tx FIFO full interrupt enable |
| RXFIFOFIE | Rx FIFO full interrupt enable |
| TXFIFOEIE | Tx FIFO empty interrupt enable |
| RXFIFOEIE | Rx FIFO empty interrupt enable |
| TXDAVLIE | Data available in Tx FIFO interrupt enable |
| RXDAVLIE | Data available in Rx FIFO interrupt enable |
| SDIOITIE | SDIO mode interrupt received interrupt enable |
| CEATAENDIE | CE-ATA command completion signal received interrupt enable |