Regviz

stm32 /stm32f4 /STM32F412 /TIM11 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UIF)UIF 0 (CC1IF)CC1IF 0 (CC1OF)CC1OF

Description

status register

Fields

UIF

Update interrupt flag
CC1IF

Capture/compare 1 interrupt flag
CC1OF

Capture/Compare 1 overcapture flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32