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stm32 /stm32f4 /STM32F413 /I2C2 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FREQ0 (ITERREN)ITERREN 0 (ITEVTEN)ITEVTEN 0 (ITBUFEN)ITBUFEN 0 (DMAEN)DMAEN 0 (LAST)LAST

Description

Control register 2

Fields

FREQ

Peripheral clock frequency
ITERREN

Error interrupt enable
ITEVTEN

Event interrupt enable
ITBUFEN

Buffer interrupt enable
DMAEN

DMA requests enable
LAST

DMA last transfer

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32