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stm32 /stm32f4 /STM32F429 /OTG_HS_HOST /OTG_HS_HFIR

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Interpret as OTG_HS_HFIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRIVL0 (RLDCTRL)RLDCTRL

Description

OTG_HS Host frame interval register

Fields

FRIVL

Frame interval
RLDCTRL

Reload control

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32