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stm32 /stm32f4 /STM32F479 /DBG /DBGMCU_APB1_FZ

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Interpret as DBGMCU_APB1_FZ

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM4_STOP)DBG_TIM4_STOP 0 (DBG_TIM5_STOP)DBG_TIM5_STOP 0 (DBG_TIM6_STOP)DBG_TIM6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_TIM12_STOP)DBG_TIM12_STOP 0 (DBG_TIM13_STOP)DBG_TIM13_STOP 0 (DBG_TIM14_STOP)DBG_TIM14_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDEG_STOP)DBG_IWDEG_STOP 0 (DBG_J2C1_SMBUS_TIMEOUT)DBG_J2C1_SMBUS_TIMEOUT 0 (DBG_J2C2_SMBUS_TIMEOUT)DBG_J2C2_SMBUS_TIMEOUT 0 (DBG_J2C3SMBUS_TIMEOUT)DBG_J2C3SMBUS_TIMEOUT 0 (DBG_CAN1_STOP)DBG_CAN1_STOP 0 (DBG_CAN2_STOP)DBG_CAN2_STOP

Description

Debug MCU APB1 Freeze registe

Fields

DBG_TIM2_STOP

DBG_TIM2_STOP
DBG_TIM3_STOP

DBG_TIM3 _STOP
DBG_TIM4_STOP

DBG_TIM4_STOP
DBG_TIM5_STOP

DBG_TIM5_STOP
DBG_TIM6_STOP

DBG_TIM6_STOP
DBG_TIM7_STOP

DBG_TIM7_STOP
DBG_TIM12_STOP

DBG_TIM12_STOP
DBG_TIM13_STOP

DBG_TIM13_STOP
DBG_TIM14_STOP

DBG_TIM14_STOP
DBG_WWDG_STOP

DBG_WWDG_STOP
DBG_IWDEG_STOP

DBG_IWDEG_STOP
DBG_J2C1_SMBUS_TIMEOUT

DBG_J2C1_SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT

DBG_J2C2_SMBUS_TIMEOUT
DBG_J2C3SMBUS_TIMEOUT

DBG_J2C3SMBUS_TIMEOUT
DBG_CAN1_STOP

DBG_CAN1_STOP
DBG_CAN2_STOP

DBG_CAN2_STOP

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32