stm32 /stm32f4 /STM32F479 /DSIHOST /DSI_DLTCR

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Interpret as DSI_DLTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MRD_TIME0LP2HS_TIME0HS2LP_TIME

Description

DSI Host data lane timer configuration register

Fields

MRD_TIME

Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.

LP2HS_TIME

Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.

HS2LP_TIME

High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.

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