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stm32 /stm32f4 /STM32F479 /DSIHOST /DSI_WPCR2

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Interpret as DSI_WPCR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TCLKPREP0TCLKZERO0THSPREP0THSTRAIL

Description

DSI Wrapper PHY configuration register 2

Fields

TCLKPREP

tCLK-PREPARE This field defines the tCLK-PREPARE has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the TCLKPREPEN bit of the DSI_WPCR0 is set. TCLKPREP = 2 x tCLK-PREPARE expressed in ns.The default value used by the D-PHY when TCLKPREPEN bit of the DSI_WPCR0 is reset is 120 (60ns + 20*UI).
TCLKZERO

tCLK-ZERO This field defines the tCLK-ZERO has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the TCLKZEROEN bit of the DSI_WPCR0 is set. TCLKZERO = tCLK-ZERO / 2 expressed in ns.The default value used by the D-PHY when TCLKZEROEN bit of the DSI_WPCR0 is reset is 195 (390ns).
THSPREP

tHS-PREPARE This field defines the tHS-PREPARE has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the THSPREPEN bit of the DSI_WPCR0 is set. THSPREP = 2 x tHS-PREPARE expressed in ns.The default value used by the D-PHY when THSPREPEN bit of the DSI_WPCR0 is reset is 126 (63ns + 12*UI).
THSTRAIL

tHSTRAIL This field defines the tHS-TRAIL has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the THSTRAILEN bit of the DSI_WPCR0 is set. THSTRAIL = 2 x tHS-TRAIL expressed in ns.The default value used by the D-PHY when THSTRAILEN bit of the DSI_WPCR0 is reset is 140 (70ns+8*UI).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32