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stm32 /stm32f4 /STM32F479 /DSIHOST /DSI_WPCR3

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Interpret as DSI_WPCR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0THSZERO0TLPXD0THSEXIT0TLPXC

Description

DSI Wrapper PHY configuration register 3

Fields

THSZERO

tHS-ZERO This field defines the tHS-ZERO has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. THSZERO = tHS-ZERO expressed in ns.The default value used by the D-PHY when THSZEROEN bit of the DSI_WPCR1 is reset is 175, (175ns).
TLPXD

tLPX for data lanes This field defines the tLPX has specified in the MIPI D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. TLPXD = 2 x tLPX expressed in ns.The default value used by the D-PHY when TLPXDEN bit of the DSI_WPCR1 is reset is 100 (50ns).
THSEXIT

tHSEXIT This field defines the tHS-EXHigh-SpeedIT has specified in the MIPI D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. THSEXIT = tHS-ZERO expressed in ns.The default value used by the D-PHY when THSEXITEN bit of the DSI_WPCR1 is reset is 100 (100ns).
TLPXC

tLPXC for clock lane This field defines the tLPX has specified in the MIPI D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. TLPXC = 2 x tLPX expressed in ns.The default value used by the D-PHY when TLPXCEN bit of the DSI_WPCR1 is reset is 100 (50ns).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32