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stm32 /stm32f7 /STM32F723 /SPI5 /I2SPR

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Interpret as I2SPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2SDIV0 (ODD)ODD 0 (MCKOE)MCKOE

Description

I2S prescaler register

Fields

I2SDIV

I2S Linear prescaler
ODD

Odd factor for the prescaler
MCKOE

Master clock output enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32