Regviz

stm32 /stm32f7 /STM32F730 /TIM13 /OR

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Interpret as OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1_RMP

Description

option register

Fields

TI1_RMP

TIM11 Input 1 remapping capability

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32