Regviz

stm32 /stm32f7 /STM32F732 /DAC /DHR12L1

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Interpret as DHR12L1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DACC1DHR

Description

channel1 12-bit left aligned data holding register

Fields

DACC1DHR

DAC channel1 12-bit left-aligned data

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32