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stm32 /stm32f7 /STM32F732 /FLASH /OPTCR

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Interpret as OPTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OPTLOCK)OPTLOCK 0 (OPTSTRT)OPTSTRT 0BOR_LEV 0 (WWDG_SW)WWDG_SW 0 (IWDG_SW)IWDG_SW 0 (nRST_STOP)nRST_STOP 0 (nRST_STDBY)nRST_STDBY 0RDP0nWRP0 (IWDG_STDBY)IWDG_STDBY 0 (IWDG_STOP)IWDG_STOP

Description

Flash option control register

Fields

OPTLOCK

Option lock
OPTSTRT

Option start
BOR_LEV

BOR reset Level
WWDG_SW

User option bytes
IWDG_SW

WDG_SW User option bytes
nRST_STOP

nRST_STOP User option bytes
nRST_STDBY

nRST_STDBY User option bytes
RDP

Read protect
nWRP

Not write protect
IWDG_STDBY

Independent watchdog counter freeze in standby mode
IWDG_STOP

Independent watchdog counter freeze in Stop mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32