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stm32 /stm32f7 /STM32F732 /RCC /AHB2ENR

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Interpret as AHB2ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AESEN)AESEN 0 (RNGEN)RNGEN 0 (OTGFSEN)OTGFSEN

Description

AHB2 peripheral clock enable register

Fields

AESEN

AES module clock enable
RNGEN

Random number generator clock enable
OTGFSEN

USB OTG FS clock enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32