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stm32 /stm32f7 /STM32F732 /SDMMC1 /ICR

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Interpret as ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCRCFAILC)CCRCFAILC 0 (DCRCFAILC)DCRCFAILC 0 (CTIMEOUTC)CTIMEOUTC 0 (DTIMEOUTC)DTIMEOUTC 0 (TXUNDERRC)TXUNDERRC 0 (RXOVERRC)RXOVERRC 0 (CMDRENDC)CMDRENDC 0 (CMDSENTC)CMDSENTC 0 (DATAENDC)DATAENDC 0 (DBCKENDC)DBCKENDC 0 (SDIOITC)SDIOITC

Description

interrupt clear register

Fields

CCRCFAILC

CCRCFAIL flag clear bit
DCRCFAILC

DCRCFAIL flag clear bit
CTIMEOUTC

CTIMEOUT flag clear bit
DTIMEOUTC

DTIMEOUT flag clear bit
TXUNDERRC

TXUNDERR flag clear bit
RXOVERRC

RXOVERR flag clear bit
CMDRENDC

CMDREND flag clear bit
CMDSENTC

CMDSENT flag clear bit
DATAENDC

DATAEND flag clear bit
DBCKENDC

DBCKEND flag clear bit
SDIOITC

SDIOIT flag clear bit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32