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stm32 /stm32f7 /STM32F746 /DMA2 /S3FCR

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Interpret as S3FCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FTH0 (DMDIS)DMDIS 0FS0 (FEIE)FEIE

Description

stream x FIFO control register

Fields

FTH

FIFO threshold selection
DMDIS

Direct mode disable
FS

FIFO status
FEIE

FIFO error interrupt enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32