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stm32 /stm32f7 /STM32F746 /OTG_FS_PWRCLK /OTG_FS_PCGCCTL

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Interpret as OTG_FS_PCGCCTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STPPCLK)STPPCLK 0 (GATEHCLK)GATEHCLK 0 (PHYSUSP)PHYSUSP

Description

OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)

Fields

STPPCLK

Stop PHY clock
GATEHCLK

Gate HCLK
PHYSUSP

PHY Suspended

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32