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stm32 /stm32f7 /STM32F746 /SPI1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXDMAEN)RXDMAEN 0 (TXDMAEN)TXDMAEN 0 (SSOE)SSOE 0 (NSSP)NSSP 0 (FRF)FRF 0 (ERRIE)ERRIE 0 (RXNEIE)RXNEIE 0 (TXEIE)TXEIE 0DS0 (FRXTH)FRXTH 0 (LDMA_RX)LDMA_RX 0 (LDMA_TX)LDMA_TX

Description

control register 2

Fields

RXDMAEN

Rx buffer DMA enable
TXDMAEN

Tx buffer DMA enable
SSOE

SS output enable
NSSP

NSS pulse management
FRF

Frame format
ERRIE

Error interrupt enable
RXNEIE

RX buffer not empty interrupt enable
TXEIE

Tx buffer empty interrupt enable
DS

Data size
FRXTH

FIFO reception threshold
LDMA_RX

Last DMA transfer for reception
LDMA_TX

Last DMA transfer for transmission

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32