Regviz

stm32 /stm32f7 /STM32F756 /ADC1 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AWD)AWD 0 (EOC)EOC 0 (JEOC)JEOC 0 (JSTRT)JSTRT 0 (STRT)STRT 0 (OVR)OVR

Description

status register

Fields

AWD

Analog watchdog flag
EOC

Regular channel end of conversion
JEOC

Injected channel end of conversion
JSTRT

Injected channel start flag
STRT

Regular channel start flag
OVR

Overrun

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32