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stm32 /stm32f7 /STM32F756 /GPIOA /BRR

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Interpret as BRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

GPIO port bit reset register

Fields

BR0

Port A Reset bit 0
BR1

Port A Reset bit 1
BR2

Port A Reset bit 2
BR3

Port A Reset bit 3
BR4

Port A Reset bit 4
BR5

Port A Reset bit 5
BR6

Port A Reset bit 6
BR7

Port A Reset bit 7
BR8

Port A Reset bit 8
BR9

Port A Reset bit 9
BR10

Port A Reset bit 10
BR11

Port A Reset bit 11
BR12

Port A Reset bit 12
BR13

Port A Reset bit 13
BR14

Port A Reset bit 14
BR15

Port A Reset bit 15

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32