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stm32 /stm32f7 /STM32F756 /OTG_HS_HOST /OTG_HS_HCSPLT0

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Interpret as OTG_HS_HCSPLT0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRTADDR0HUBADDR0XACTPOS 0 (COMPLSPLT)COMPLSPLT 0 (SPLITEN)SPLITEN

Description

OTG_HS host channel-0 split control register

Fields

PRTADDR

Port address
HUBADDR

Hub address
XACTPOS

XACTPOS
COMPLSPLT

Do complete split
SPLITEN

Split enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32