status register
| CCRCFAIL | Command response received (CRC check failed) |
| DCRCFAIL | Data block sent/received (CRC check failed) |
| CTIMEOUT | Command response timeout |
| DTIMEOUT | Data timeout |
| TXUNDERR | Transmit FIFO underrun error |
| RXOVERR | Received FIFO overrun error |
| CMDREND | Command response received (CRC check passed) |
| CMDSENT | Command sent (no response required) |
| DATAEND | Data end (data counter, SDIDCOUNT, is zero) |
| STBITERR | Start bit not detected on all data signals in wide bus mode |
| DBCKEND | Data block sent/received (CRC check passed) |
| CMDACT | Command transfer in progress |
| TXACT | Data transmit in progress |
| RXACT | Data receive in progress |
| TXFIFOHE | Transmit FIFO half empty: at least 8 words can be written into the FIFO |
| RXFIFOHF | Receive FIFO half full: there are at least 8 words in the FIFO |
| TXFIFOF | Transmit FIFO full |
| RXFIFOF | Receive FIFO full |
| TXFIFOE | Transmit FIFO empty |
| RXFIFOE | Receive FIFO empty |
| TXDAVL | Data available in transmit FIFO |
| RXDAVL | Data available in receive FIFO |
| SDIOIT | SDIO interrupt received |
| CEATAEND | CE-ATA command completion signal received for CMD61 |