Regviz

stm32 /stm32f7 /STM32F768 /CEC /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CECEN)CECEN 0 (TXSOM)TXSOM 0 (TXEOM)TXEOM

Description

control register

Fields

CECEN

CEC Enable
TXSOM

Tx start of message
TXEOM

Tx End Of Message

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32