Regviz

stm32 /stm32f7 /STM32F768 /DSI /DSI_CLCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_CLCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f7/STM32F767/DSI/DSI_CLCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DPCC)DPCC 0 (ACR)ACR

Description

DSI Host Clock Lane Configuration Register

Fields

DPCC

D-PHY Clock Control
ACR

Automatic Clock lane Control

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32