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stm32 /stm32f7 /STM32F768 /FMC /SDSR

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Interpret as SDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE)RE 0MODES1 0MODES2 0 (BUSY)BUSY

Description

SDRAM Status register

Fields

RE

Refresh error flag
MODES1

Status Mode for Bank 1
MODES2

Status Mode for Bank 2
BUSY

Busy status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32