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stm32 /stm32f7 /STM32F768 /LTDC /SRCR

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Interpret as SRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IMR)IMR 0 (VBR)VBR

Description

Shadow Reload Configuration Register

Fields

IMR

Immediate Reload
VBR

Vertical Blanking Reload

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32