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stm32 /stm32f7 /STM32F777 /DSI /DSI_PSR

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Interpret as DSI_PSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PD)PD 0 (PSSC)PSSC 0 (UANC)UANC 0 (PSS0)PSS0 0 (UAN0)UAN0 0 (RUE0)RUE0 0 (PSS1)PSS1 0 (UAN1)UAN1

Description

DSI Host PHY Status Register

Fields

PD

PHY Direction
PSSC

PHY Stop State Clock lane
UANC

ULPS Active Not Clock lane
PSS0

PHY Stop State lane 0
UAN0

ULPS Active Not lane 1
RUE0

RX ULPS Escape lane 0
PSS1

PHY Stop State lane 1
UAN1

ULPS Active Not lane 1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32