DSI Wrapper PHY Configuration Register 1
| UIX4 | Unit Interval multiplied by 4 |
| SWCL | Swap Clock Lane pins |
| SWDL0 | Swap Data Lane 0 pins |
| SWDL1 | Swap Data Lane 1 pins |
| HSICL | Invert Hight-Speed data signal on Clock Lane |
| HSIDL0 | Invert the Hight-Speed data signal on Data Lane 0 |
| HSIDL1 | Invert the High-Speed data signal on Data Lane 1 |
| FTXSMCL | Force in TX Stop Mode the Clock Lane |
| FTXSMDL | Force in TX Stop Mode the Data Lanes |
| CDOFFDL | Contention Detection OFF on Data Lanes |
| TDDL | Turn Disable Data Lanes |
| PDEN | Pull-Down Enable |
| TCLKPREPEN | custom time for tCLK-PREPARE Enable |
| TCLKZEROEN | custom time for tCLK-ZERO Enable |
| THSPREPEN | custom time for tHS-PREPARE Enable |
| THSTRAILEN | custom time for tHS-TRAIL Enable |
| THSZEROEN | custom time for tHS-ZERO Enable |
| TLPXDEN | custom time for tLPX for Data lanes Enable |
| THSEXITEN | custom time for tHS-EXIT Enable |
| TLPXCEN | custom time for tLPX for Clock lane Enable |
| TCLKPOSTEN | custom time for tCLK-POST Enable |