DSI_WPCR2

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Interpret as DSI_WPCR2

DSI Wrapper PHY Configuration Register 2

HSTXDCL	High-Speed Transmission Delay on Clock Lane
HSTXDLL	High-Speed Transmission Delay on Data Lanes
LPSRCL	Low-Power transmission Slew Rate Compensation on Clock Lane
LPSRDL	Low-Power transmission Slew Rate Compensation on Data Lanes
SDCC	SDD Control
HSTXSRCCL	High-Speed Transmission Slew Rate Control on Clock Lane
HSTXSRCDL	High-Speed Transmission Slew Rate Control on Data Lanes
FLPRXLPM	Forces LP Receiver in Low-Power Mode
LPRXFT	Low-Power RX low-pass Filtering Tuning

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