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stm32 /stm32f7 /STM32F778 /DFSDM /DFSDM_CHCFG3R2

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Interpret as DFSDM_CHCFG3R2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTRBS0OFFSET

Description

DFSDM channel configuration 3 register 2

Fields

DTRBS

Data right bit-shift for channel 3
OFFSET

24-bit calibration offset for channel 3

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32