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stm32 /stm32f7 /STM32F778 /LPTIM1 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (SNGSTRT)SNGSTRT 0 (CNTSTRT)CNTSTRT

Description

Control Register

Fields

ENABLE

LPTIM Enable
SNGSTRT

LPTIM start in single mode
CNTSTRT

Timer start in continuous mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32