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stm32 /stm32f7 /STM32F778 /SAI1 /BCLRFR

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Interpret as BCLRFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVRUDR)OVRUDR 0 (MUTEDET)MUTEDET 0 (WCKCFG)WCKCFG 0 (CNRDY)CNRDY 0 (CAFSDET)CAFSDET 0 (LFSDET)LFSDET

Description

BClear flag register

Fields

OVRUDR

Clear overrun / underrun
MUTEDET

Mute detection flag
WCKCFG

Clear wrong clock configuration flag
CNRDY

Clear codec not ready flag
CAFSDET

Clear anticipated frame synchronization detection flag
LFSDET

Clear late frame synchronization detection flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32