stm32 /stm32f7 /STM32F779 /ADC_Common /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AWD1)AWD1 0 (EOC1)EOC1 0 (JEOC1)JEOC1 0 (JSTRT1)JSTRT1 0 (STRT1)STRT1 0 (OVR1)OVR1 0 (AWD2)AWD2 0 (EOC2)EOC2 0 (JEOC2)JEOC2 0 (JSTRT2)JSTRT2 0 (STRT2)STRT2 0 (OVR2)OVR2 0 (AWD3)AWD3 0 (EOC3)EOC3 0 (JEOC3)JEOC3 0 (JSTRT3)JSTRT3 0 (STRT3)STRT3 0 (OVR3)OVR3

Description

ADC Common status register

Fields

AWD1

AWD1

EOC1

EOC1

JEOC1

JEOC1

JSTRT1

JSTRT1

STRT1

STRT1

OVR1

OVR1

AWD2

AWD2

EOC2

EOC2

JEOC2

JEOC2

JSTRT2

JSTRT2

STRT2

STRT2

OVR2

OVR2

AWD3

AWD3

EOC3

EOC3

JEOC3

JEOC3

JSTRT3

JSTRT3

STRT3

STRT3

OVR3

OVR3

Links

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