Regviz

stm32 /stm32g0 /STM32G031 /WWDG /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0T0 (WDGA)WDGA

Description

Control register

Fields

T

7-bit counter (MSB to LSB)
WDGA

Activation bit

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32