Regviz

stm32 /stm32g0 /STM32G041 /ADC /CHSELR_1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHSELR_1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32g0/STM32G031/ADC/CHSELR_1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SQ10SQ20SQ30SQ40SQ50SQ60SQ70SQ8

Description

channel selection register CHSELRMOD = 1 in ADC_CFGR1

Fields

SQ1

conversion of the sequence
SQ2

conversion of the sequence
SQ3

conversion of the sequence
SQ4

conversion of the sequence
SQ5

conversion of the sequence
SQ6

conversion of the sequence
SQ7

conversion of the sequence
SQ8

conversion of the sequence

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32