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stm32 /stm32g0 /STM32G041 /LPTIM1 /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IN1SEL 0IN2SEL

Description

LPTIM configuration register 2

Fields

IN1SEL

LPTIMx Input 1 selection
IN2SEL

LPTIM1 Input 2 selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32