Regviz

stm32 /stm32g0 /STM32G051 /TIM6 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UIF

UIF=B_0x0

Description

status register

Fields

UIF

Update interrupt flag

0 (B_0x0): No update occurred.

1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated:

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32