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stm32 /stm32g0 /STM32G061 /FLASH /OPTR

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Interpret as OPTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDP0 (BOREN)BOREN 0BORF_LEV 0BORR_LEV 0 (nRST_STOP)nRST_STOP 0 (nRST_STDBY)nRST_STDBY 0 (nRSTS_HDW)nRSTS_HDW 0 (IDWG_SW)IDWG_SW 0 (IWDG_STOP)IWDG_STOP 0 (IWDG_STDBY)IWDG_STDBY 0 (WWDG_SW)WWDG_SW 0 (RAM_PARITY_CHECK)RAM_PARITY_CHECK 0 (nBOOT_SEL)nBOOT_SEL 0 (nBOOT1)nBOOT1 0 (nBOOT0)nBOOT0 0NRST_MODE 0 (IRHEN)IRHEN

Description

Flash option register

Fields

RDP

Read protection level
BOREN

BOR reset Level
BORF_LEV

These bits contain the VDD supply level threshold that activates the reset
BORR_LEV

These bits contain the VDD supply level threshold that releases the reset.
nRST_STOP

nRST_STOP
nRST_STDBY

nRST_STDBY
nRSTS_HDW

nRSTS_HDW
IDWG_SW

Independent watchdog selection
IWDG_STOP

Independent watchdog counter freeze in Stop mode
IWDG_STDBY

Independent watchdog counter freeze in Standby mode
WWDG_SW

Window watchdog selection
RAM_PARITY_CHECK

SRAM parity check control
nBOOT_SEL

nBOOT_SEL
nBOOT1

Boot configuration
nBOOT0

nBOOT0 option bit
NRST_MODE

NRST_MODE
IRHEN

Internal reset holder enable bit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32