Regviz

stm32 /stm32g0 /STM32G070 /TIM14 /TISEL

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Interpret as TISEL

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https://regviz.com/r/stm32/stm32g0/STM32G030/TIM14/TISEL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TISEL

Description

TIM timer input selection register

Fields

TISEL

TI1[0] to TI1[15] input selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32