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stm32 /stm32g0 /STM32G071 /RTC /MISR

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Interpret as MISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALRAMF)ALRAMF 0 (ALRBMF)ALRBMF 0 (WUTMF)WUTMF 0 (TSMF)TSMF 0 (TSOVMF)TSOVMF 0 (ITSMF)ITSMF

Description

masked interrupt status register

Fields

ALRAMF

ALRAMF
ALRBMF

ALRBMF
WUTMF

WUTMF
TSMF

TSMF
TSOVMF

TSOVMF
ITSMF

ITSMF

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32