Regviz

stm32 /stm32g0 /STM32G071 /TIM2 /AF1

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Interpret as AF1

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https://regviz.com/r/stm32/stm32g0/STM32G030/TIM2/AF1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ETRSEL

Description

TIM alternate function option register 1

Fields

ETRSEL

External trigger source selection

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32